A memory chip generally comprises a plurality of memory cells that are deposited onto a silicon wafer and addressable via an array of column conducting leads (bit lines) and row conducting leads (word lines). Typically, a memory cell is situated at the intersection of a bit line and a word line. The memory cells are controlled by specialized circuits that perform functions such as identifying rows and columns from which data are read or to which data are written. Typically, each memory cell stores data in the form of a “1” or a “0,” representing a bit of data.
An array of magnetic memory cells can be referred to as a magnetic random access memory or MRAM. MRAM is generally nonvolatile memory (i.e., a solid state chip that retains data when power is turned off). At least one type of magnetic memory cell includes a data layer and a reference layer, separated from each other by at least one intermediate layer. The data layer may also be referred to as a bit layer, a storage layer, or a sense layer. The reference layer may also be referred to as a pinned layer. In a magnetic memory cell, a bit of data (e.g., a “1” or “0”) may be stored by “writing” into the data layer via one or more conducting leads (e.g., a bit line and a word line). The write operation is typically accomplished via a write current that sets the orientation of the magnetic moment in the data layer to a predetermined direction.
Once written, the stored bit of data may be read by providing a read current through one or more conducting leads (e.g., a read line) to the magnetic memory cell. For each memory cell, the orientations of the magnetic moments of the data layer and the reference layer are either parallel (in the same direction) or anti-parallel (in different directions) to each other. The degree of parallelism affects the resistance of the cell, and this resistance can be determined by sensing (e.g., via a sense amplifier) an output current or voltage produced by the memory cell in response to the read current.
More specifically, if the magnetic moments are parallel, the resistance determined based on the output current is of a first relative value (e.g., relatively low). If the magnetic moments are anti-parallel, the resistance determined is of a second relative value (e.g., relatively high). The relative values of the two states (i.e., parallel and anti-parallel) are typically different enough to be sensed distinctly. A “1” or a “0” may be assigned to the respective relative resistance values depending on design specification. The sensed current is inversely proportional to the resistance of the magnetic memory cell. Thus, Is=V/R (when magnetic moments are parallel) or Is=V/(R+ΔR) (when magnetic moments are anti-parallel), where V is the applied voltage, Is is the sensed current, R is the nominal resistance of the magnetic memory cell, and ΔR is the change in resistance.
The intermediate layer, which may also be referred to as a spacer layer, may comprise insulating material (e.g., dielectric), non-magnetic conducting material, and/or other known materials, and is usually thick enough to prevent exchange coupling between the data and reference layers. The various conducting leads which are used to address the memory cells (e.g., bit lines, word lines, and read lines), and to provide currents to pass through the data and reference layers to read data from or write data to the memory cells are provided by one or more additional layers, called conducting layer(s).
Throughout this application, various exemplary embodiments will be described in reference to the TMR memory cells as first described above. Those skilled in the art will readily appreciate that the exemplary embodiments may also be implemented with other types of magnetic memory cells (e.g., other types of TMR memory cells, GMR memory cells, AMR memory cells, CMR memory cells, etc.) according to the requirements of a particular implementation.
Generally speaking, desirable characteristics for any configuration of memory device include increased speed, reduced power consumption, and/or lower cost. A simpler fabrication process and/or a smaller chip size may achieve lower cost. However, as magnetic memory cells become smaller, typically, higher operating current is required for achieving “write” operations. FIG. 1 illustrates some exemplary relationships between various aspect ratios (at a fixed thickness) of a ferromagnetic layer and their coercivities. As shown in FIG. 1, magnetic coercivity increases as memory cell area decreases. As a result, an increased write current is generally needed to reverse the magnetic orientations of one or more layers of the memory cell. Higher operating current is undesirable because it goes hand-in-hand with higher power requirements, increased concern about electromigration, increased write circuitry area, and increased cost. One way to reduce the coercivity in a small magnetic memory cell is to reduce the thicknesses of the ferromagnetic layers. However, as the total magnetic volume decreases, the magnetic memory cell also becomes less thermally stable. FIG. 2 illustrates some exemplary relationships between temperature and the coercivities of ferromagnetic layers at various thicknesses (at a fixed lateral area).
Thus, a market exists for a multi-layered magnetic memory structure that has improved thermal stability as well as reduced coercivity.